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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
2.5.7
SPI Terminal Functions
Table 2-11. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
Serial Port Interface (SPI)
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS0_E0/
SPI_CS0
P4
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
P11
I/O/Z
IPD
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS1_E1/
SPI_CS1
N4
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS1.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RW_WRB/
SPI_CS2
P5
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS2.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RS/
SPI_CS3
N5
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS3.
This pin is multiplexed between LCD Bridge and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
LCD_EN_RDB/
SPI_CLK
N3
O/Z
DV DDIO
BH
Note: This pin may consume static power if configured as Hi-Z and not pulled high
or low. Prevent current drain by externally terminating the pin.
This pin is ONLY in the Hi-Z state when doing boundary scan. Therefore, external
termination is probably not required for most applications.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D8]/
I2S2_CLK/
GP[18]/
SPI_CLK
N10
I/O/Z
IPD
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[1]/
SPI_TX
N6
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
P12
I/O/Z
IPD
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[0]/
SPI_RX
P6
I/O/Z
DV DDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
(1)
(2)
(3)
(4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors .
Specifies the operating I/O supply voltage for each signal
28
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